Careers

Build your career with Sykatiya Technologies

Sykatiya Technologies, believes in Technical Ability along with the Attitude of our highly talented team and reflects the same in the contributions to the customers’ project. Team comprises highly talented engineers and experts from Design Verification, DFT/Test, Physical Design and Analog Design for ASICs.

IP/SOC /ASIC Verification

Experience: 3-20 Years

Location: Bangalore & Hyderabad

In this role, you will be part of the ASIC verification team responsible for functional verification of ASIC IPs. ASIC verification methodology employs state of the art techniques and tools, including coverage-driven constrained random verification and formal verification. Object-oriented architectures and frameworks are a fundamental part of how we design and implement our verification environments.
Expertise and Aptitude towards verifying functions such as image processing, video compression, and computer vision. As a verification engineer, you will also have the opportunity to learn about the algorithms behind the hardware.


Who Are We Looking For?

We are looking for an experienced engineer with an exceptional talent for programming and a genuine interest in ASIC verification. Our verification environments are often quite elaborate, so you must have an aptitude for understanding, implementing, and maintaining complex software systems.
Prior experience in hardware verification using SystemVerilog, UVM, low power verification, and formal methods are desirable.
As a person, we believe you are analytical, systematic, and have attention to detail.

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Analog Design engineer

Experience: 3-12 Years

Location: Bangalore

  • Experience in transceiver design for high-speed interface such as DDR, HBM, PCIe, USB3, JESD204
  • Exposure to node below 22nm is plus
  • Experience in FINFET technology and 32G-112G range of SERDES is preferred.
  • Candidate should have taken at least one block from circuit design to layout closure
  • Candidate should be able to guide the layout team for high performance matched circuit design
  • Candidate should understand the reliability requirements such as ESD, EMIR, EOS, Aging etc
  • Candidate should be able to work independently and mentor the juniors
  • Exposure to post silicon validation is plus
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IO Design

Experience: 3-8 Years

Location: Bangalore

  • Should have led a team on development of atleast 1 IO library from spec to GDS.
  • Good knowledge of all the collateral views, their QA & should be able to review the collaterals
  • Should be able to guide the layout team on the design constraints & should be able to do the layout reviews
  • Should have worked on Finfet nodes, good knowledge of reliability concepts like Aging, HCI, BTI & EOS
  • Good knowledge of IO ring level care-about : supply sequencing, ESD, SSO/SSI, R-bus, Supply-to-power pad ratio & jitter analysis
  • Candidate should be able to lead the project
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RTL/ IP Design

Experience: 3-12 Years

Location: Bangalore

  • You have 5+ years of experience of digital ASIC front-end design
  • Have a good understanding of the design flow like RTL (VHDL, Verilog and/or SystemVerilog)
  • Have experience of simulation tools like Questa or Xcelium and logic synthesis (e.g. Synopsys DC).
  • You have experience of embedded microcontrollers and AMBA bus systems.
  • You have a science/engineering Bachelor's degree and you speak English fluently.
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Back end STA/Synthesis

Experience: 3-12 Years

Location: Bangalore

  • 5-12 years of experience in ASIC Physical synthesis/STA
  • Expertise in Synopsys/Cadence Synthesis tools
  • Expertise with STA with prime time/Tempus.
  • Good Experience in synthesis timing closure and interactions with DFT and PD.
  • Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
  • Experience in formal verification with Cadence LEC
  • Expertise in ECO flows using conformal/Formality ECO.
  • Experience in Spyglass Lint/CDC checks and waiver creation
  • Experience in RTL HDL languages Verilog/VHDL.
  • Understanding of RTL to GDS flow
  • Expertise in Perl, TCL language
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Freelancer

Sykatiya Technologies, believes in Technical Ability along with the Attitude of our highly talented team and reflects the same in the contributions to the customers’ project. Team comprises highly talented engineers and experts from Design Verification, DFT/Test, Physical Design and Analog Design for ASICs.

Freelancer

  • Sykatiya Technologies encourages "Free Lancers" who are mature individuals and domain experts
  • Domain experts in RTL, DV, DFT, Physical Design, STA, IR Drop Analysis and Physical verification
  • Minimum experience: 8 Years and specialized in their domains
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