Solutions

Turnkey ASIC

Strong expertise and able techno-leadership in all the domains from RTL Integration, Synthesis, DFT and Physical Design come together to make sure customer design is owned, planned, executed and signed-off as per customer choice.



1) Standard / Conventional Turnkey Execution

  • RTL Integration & Checks
  • Synthesis / Physical Synthesis and Pre-Layout STA
  • DFT architecture definition
  • Test Architecture definition
  • DFT implementation, ATPG and Debug
  • Post-Si Debug Support
  • Power Plan, Floor Plan, CTS, PnR and PV
  • Power Analysis
  • STA and PV Sign-Off
  • TSMC/GF/Samsung/Intel FABs from 7nm to 250nm
  • Effective Techno-Management leadership to plan, track and execute
    • Risk Mitigation
  • Technology Node (TSMC/GF/Samsung/Intel): 5nm, 7nm, 16nm, 22nm, 28nm,40nm, 65nm. 90nm, 130nm, 180nm and 250nm

2) Value-Added Solutions

Ultra Low Power Optimization Technology (Synthesis – PD)

  • Seamless integration with standard flows
  • PPA enhancement
  • Power: About 40% improvement over the standard flow PPA
  • Area: About 20% improvement over the standard flow PPA
    • For a given Frequency
  • Target Applications: AI & Edge Devices , Wireless, Servers / Data Centres
  • Target Designs: Highly Data Path Intensive Designs, Processors, Neural Network Processing Elements, Matrix Multipliers, NOC/MESH designs

Features – Seamless Integration

  • Complements Customers Conventional / Standard golden Flow
  • Context Aware (proprietary IP)
  • Advanced Data Path Architecture and Algorithm
  • Agnostic to Tool/Flow/Tech Node / Application
  • Minimal- zero overhead on Verification & Timelines

Test - Chip Execution

  • Constraints Dev-Synthesis-DFT-Physical Design Architecture Definition
  • Tools: In-House
  • Sign-Off
  • FAB: Relationship and Interface

Standalone Solutions

  • Design Verification
    • UVM based TB Architecture definition
    • Implementation at Block and SoC Level
    • Mixed Signal Verification
  • DFT
    • DFT- TEST Architecture Definition & Implementation
    • Auto design generation, Integration and create DFT, DV,PD, STA, Package and Test infrastructure
    • ATPG & Debug , Sign-off
  • RTL2GDS Implementation
  • Analog Design & Layout
    • End-to-End Analog Mixed Signal Design and Layout at IP and SoC level
    • HS SerDes, Power managements(LDO), Data Converters, Reference Design, Temperature Sensors, OPAMPs, Comparators and other complex Analog Mixed Signal Circuits

IC Design Services

We offer design services to complement your team and to accelerate your analog, digital or custom ASIC / SoC projects.

Digital

  • RTL Integration
  • Design Verification
  • DFT
  • Physical Design

Analog

  • Circuit Design
  • Layout
  • Mixed Signal Verification
  • Standard Cell Design and Characterization

Post Silicon Validation

  • Functional Validation
  • Electrical Characteristics Compliance
  • High Speed Protocols
  • USB2.0, USB4, HDMI
  • MRAM
  • Analog & Digital Interfaces, PVT
  • Product Engineering (PDE)
  • Post-Silicon Validation (PSV)

Test & Product Engineering

  • PCB Design
  • ATE Debug/Bring-up
  • Product Engineering (PDE)
  • Post-Silicon Validation (PSV)

Engagement Models

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